The present invention relates to a semiconductor device.
Portable electronic devices, such as cellular phones, PDAs, DVCs, and DSCs, have become to be provided with a larger number of functions. Further, there are demands for compact and portable electronic devices. To satisfy such demands, highly integrated system LSIs are necessary.
One example of a module that realizes a high integration system LSI is a high frequency bipolar transistor. To increase the performance of a high frequency high polar transistor, a silicon-germanium (SiGe) heterojunction bipolar transistor has been proposed. Japanese Laid-Open Patent Publication No. 4-179235 describes the manufacturing of a bipolar transistor in the prior art.
The manufacturing of an SiGe heterojunction bipolar transistor will now be described with reference to FIGS. 13 and 14.
Referring to FIG. 13, an n+ type collector embedment layer 101 is formed on a p− type silicon substrate (not shown). An n− type layer 102 (epitaxial layer), which functions as a collector layer, is formed on the n+ type collector embedment layer 101. The n− type layer 102 is etched and removed excluding portions required for use as the collector layer and a collector extraction layer. An element isolation region includes a trench, of which the surface is covered by an oxidation film 103, and a polycrystalline silicon film 104, which is embedded in the trench. After the formation of the collector and element isolation region, a flat oxidation film 105 (embedment oxidation film) is formed on the surface of the substrate. A p-type SiGe layer 106 (SiGe alloy layer), which functions as an internal base layer, is formed on the oxidation film. Then, an n-type silicon layer 107, which functions as an emitter layer, and an n+ type silicon layer 108, which functions as an emitter-contact layer (emitter electrode), are epitaxially grown on the p-type SiGe layer 106. While using an oxidation film 109 as a mask, the n+ type silicon layer 108 and the n-type silicon layer 107 are etched and removed excluding portions required to form the emitter. The outer side of the region functioning as the internal base layer in the residual p-type SiGe layer 106 is etched for a predetermined depth using an oxidation film (side wall film) 110 and the oxidation film 109 as masks. This portion then undergoes selective epitaxial growth to form a p+ type SiGe layer 111, which functions as an external base layer.
In the SiGe base heterojunction bipolar transistor configuration of the prior art, the n-type silicon layer 107 (emitter layer) includes a relatively narrow upper surface and a relatively wide lower surface. The width of the lower surface of the emitter layer is about the same as the outer dimension (We2) of the side wall film 110. Accordingly, the width We2 of the emitter-base junction, which is located below the n-type silicon layer 107, is much greater than the width We1 of the n+ type silicon layer 108 (emitter electrode).
To manufacture a semiconductor device (SiGe base heterojunction bipolar transistor) having higher capacities, the n+ type silicon layer 108 (emitter electrode) must further be processed in a miniaturized manner to decrease the width We1, which would further decrease the width We2 of the emitter layer. However, this would result in the need of a highly accurate exposure apparatus and thus increase manufacturing costs.